ADT7490
Table 68. FAN TACHOMETER LIMIT REGISTERS (Note 1)
Register Address
0x34
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
PECI Low Limit
TACH1 Minimum Low Byte
TACH1 Minimum High Byte/Single-channel ADC Channel Select
TACH2 Minimum Low Byte
TACH2 Minimum High Byte
TACH3 Minimum Low Byte
TACH3 Minimum High Byte
TACH4 Minimum Low Byte
TACH4 Minimum High Byte
Power-On Default
0x81
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
1. Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set
in Interrupt Status Register 2 (0x42) to indicate fan failure. Setting the Configuration Register 1 (0x40) Lock bit has no effect on these
registers.
Table 69. REGISTER 0 x55 ? TACH 1 MINIMUM HIGH BYTE (POWER-ON DEFAULT = 0xFF)
Bit No.
[3:0]
[7:4]
Mnemonic
Reserved
SCADC
R/W
Read-only
R/W
Description
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits
are reserved. Otherwise, these bits represent Bits [3:0] of the TACH1 minimum high byte.
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits
are used to select the only channel from which the ADC will take measurements. Otherwise,
these bits represent Bits [7:4] of the TACH1 minimum high byte.
Bit Code Single-channel Select
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Table 70. PWM CONFIGURATION REGISTERS
+2.5 V IN
V CCP
V CC
+5 V IN
+12 V IN
Remote 1 Temperature
Local Temperature
Remote 2 Temperature
V TT
I MON
Register Address
0x34
0x5C
0x5D
0x5E
R/W (Note 1)
R/W
R/W
R/W
R/W
Description
PECI Low Limit
PWM1 Configuration
PWM2 Configuration
PWM3 Configuration
Power-On Default
0x81
0x62
0x62
0x62
1. These registers become read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any subsequent attempts to write to these
registers fail.
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